1. Field of the Invention
The present invention relates to a delay line and a memory control circuit utilizing the delay line, and more particularly, to a delay line implemented by a Pseudo NMOS transistor and a memory control circuit utilizing the delay line.
2. Description of the Prior Art
In many kinds of circuits, a delay locked loop (DLL) circuit is utilized for synchronizing clock(s) to prevent errors resulting from non-synchronization.
Please refer to FIG. 1a in conjunction with FIG. 1b and FIG. 2. FIG. 1a is a block diagram illustrating a prior art analog DLL circuit and FIG. 2 is a schematic diagram illustrating the general operation of the analog DLL circuit shown in FIG. 1a. The analog DLL circuit 100 includes a plurality of delay cells 101-107, a phase detector 109, a charge pump 111, and a loop filter 113. The delay cells 101-107 are used for delaying the input clock signal CKin to generate an output clock signal CKn synchronized with the input clock CKin. The delay cells 101-107 form a delay line. Furthermore, the delay cells 101-107 generate clock signals having different delay amounts, such as CK1, CK2 . . . , CKn as shown in FIG. 2, where each of the clock signals CK1, CK2 . . . , CKn may be extracted from the DLL circuit if necessary. In this case, the number of delay cells is n, thus the delay amount of each delay cell 101-107 is the total delay amount between the input clock signal CKin and the output clock signal CKn divided by n.
The phase detector 109, the charge pump 111, and the loop filter 113 form a control circuit for controlling the delay cells 101-107. The phase detector 109 is utilized for comparing the input signal CKin with the output signal CKn to generate an up signal UP and a down signal DN. The up signal UP and the down signal DN inform the charge pump 111 and the loop filter 113 to generate a control voltage Vctrl for controlling the operation of the delay cells 101-107. Since the operation of the charge pump 111 and the loop filter 113 is well known to persons skilled in the art, further description is omitted for brevity. In this way, the delay amount of the delay cells 101-107 may be adjusted to enable the output signal CKn to synchronize with the input signal CKin; that is, the delay amount D1 between the input clock signal CKin and the output clock signal CKn is equal to one period of the input clock signal CKin.
FIG. 1b is a block diagram illustrating a prior art digital DLL circuit 121. The digital DLL circuit 121 includes a delay line 123, which is formed by a plurality of delay cells 125, a phase detector 127, and a DLL controller 129. Each of the delay cells 125 is used for providing a predetermined delay amount dt. Therefore, if the number of delay cells 125 in the delay line 123 is K, the total amount of the delay time on the input clock CLKi is equal to K*dt. A delayed clock CLKd and the input clock CLKi are delivered to the phase detector 127. The prior art phase detector 127 outputs a notification signal Sc to the DLL controller 129 when a 180° phase difference (i.e. a phase change) between the delayed clock CLKd and the input clock CLKi is detected twice. That is, the notification signal Sc informs the DLL controller 129 of the situation that the delayed clock CLKd is lagging 360° behind the input clock CLKi. Therefore, the DLL controller 129 continuously programs the amount of delay dt of each delay cell 125 to increase the total amount of delay on the input clock CLKi until the notification signal Sc is generated from the phase detector 127. The DLL controller 129 can further have a digital loop filter 131 included therein.
The prior art technique utilizes complementary metal oxide semiconductor (CMOS) transistors to implement the delay cells 101-107. However, the CMOS transistor has a relatively large delay amount; therefore, it will cause output signal jitter in the high-frequency signal and further affect the resolution of the DLL.